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PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
Z86E73/E74 32K OTP Z86L73/L74 32K ROM
INFRARED REMOTE CONTROLLERS
FEATURES
Part Z86E73 Z86L73 Z86E74 Z86L74 ROM (Kbyte) 32 32 32 32 RAM* One-Time (Kbyte) Programmable 1004 Yes 492 No 1004 Yes 1004 No Speed (MHz) 8 8 8 8
s s
Expanded Register Files (ERF) 31 Input/Output Lines (E73/L73) 51 Input/Output Lines (E74/L74*)
*Note: With Auto Latch on Port 4, 5 and 6.
* General-Purpose
s s s
Five Prioritized Interrupts with Programmable Polarity Two Comparators 8-Bit Counter/Timer with Two Capture Registers and 16-Bit Counter/Timer with One Capture Register Watch-Dog Timer (WDT)/Power-On Reset (POR) On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive Low-Voltage Detection and Protection 32-KHz Mask Option to Disable Internal Feedback Resistor (L73/L74)
s
40-Pin DIP, 44-Pin PLCC/QFP Packages (E73/L73) 64-Pin DIP, 68-Pin PLCC Packages (E74/L74) 2.0V to 3.9V Operating Range (L73/L74) 4.5V to 5.5V Operating Range (E73/E74)
s
s s
Low-Power Consumption (Typical: 40 mw for L73/L74) (Typical: 60 mw for E73/E74) 0C to +70C Temperature Range
s
s
s s
GENERAL DESCRIPTION
The Z86E73/L73/E74/L74 are ROM-based members of Zilog's Z8(R) single-chip microcontroller family of infrared (IR) consumer controller processors featuring fast and flexible code execution. The Z86E73/E74 devices offer a one-time programmable (OTP) option. For applications demanding powerful I/O capabilities, the Z86E73/L73's dedicated input and output lines are grouped into four ports, and into seven ports for the Z86E74/L74. They are configurable under software control to provide timing, status signals, or parallel I/O. Four address spaces, the Program Memory, Register File, Data Memory, and Expanded Register File (ERF) support a wide range of memory configurations. Through the ERF the designer has access to three additional control registers that provide extra peripheral devices, I/O ports, and register addresses. Two on-chip counter/timers, with a large number of selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O datacommunications.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD
VSS
CP95LVO0801
1
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
GENERAL DESCRIPTION (Continued)
P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27
I/O Bit Programmable
4
Register File 512 or 1K x 8-bit Port 0 Register Bus Port 3 Internal Address Bus ROM 16K/32K x 8 Internal Data Bus Z8 Core
P31 P32 P33 P34 P35 P36 P37
4
8
Port 1 Extended Register File Extended Register Bus
Machine Timing & Instruction Control
XTAL /AS /DS R/W /RESET
Port 2 Counter/Timer 8 8-Bit Counter/Timer 16 16-Bit
Power
VDD VSS
Port 4
8 Z86E74/L74 version only
Port 5
8
Port 6
4
Functional Block Diagram
2
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
PIN DESCRIPTION
R//W P25 P26 P27 P04 P05 P06 P14 P15 P07 VDD P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 /AS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Z86E73/L73 DIP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
/DS P24 P23 P22 P21 P20 P03 P13 P12 VSS P02 P11 P10 P01 P00 Pref1 P36 P37 P35 /RESET
P56 R/W P25 P26 P27 P04 P05 P06 P14 P15 P07 VDD VDD P40 P41 P42 P43 P44 P45 P16 P17 XTAL2 XTAL1 P31 P32 P33 P34
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
R//RL P54 P53 /DS P51 P50 P24 P23 P22 P21 P20 P03 P13 P12 VSS VSS P52 P57 P02 P46 P47 P11 P10 P01 P00 PREF1 P36 P37 P35 /RESET VSS P62
Z86E74/L74 DIP
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Z86E73 (Standard Mode) Z86L73 40-Pin DIP Pin Assignments
P60 P61 /AS P63 P55
Z86E74 (Standard Mode) Z86L74 64-Pin DIP Pin Assignments
3
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
PIN DESCRIPTION
P03 P13 P12 VSS VSS P20 P02 P11 P10 P01 P00 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 VDD VDD P16 P17 XTAL2 XTAL1 P05 P06 P14 P15 P07
65432 P21 P22 P23 P24 /DS R//RL R//W P25 P26 P27 P04 7 8 9 10 11 12 13 14 15 16 17
1 44 43 42 41 40 Pref1 P36 P37 P35 /RESET VSS /AS P34 P33 P32 P31
Z86E73/L73 PLCC
Z86E73 (Standard Mode) Z86L73 44-Pin PLCC Pin Assignments
P21 P22 P23 P24 /DS R//RL R//W P25 P26 P27 P04
34 35 36 37 38 39 40 41 42 43 44
P20 P03 P13 P12 VSS VSS P02 P11 P10 P01 P00
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Pref1 P36 P37 P35 /RESET VSS /AS P34 P33 P32 P31
Z86E73/L73 QFP
1 2 3 4 5 6 7 8 9 10 11
Z86E73 (Standard Mode) Z86L73 44-Pin QFP Pin Assignments
4
VDD VDD P16 P17 XTAL2 XTAL1
P05 P06 P14 P15 P07
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
PIN DESCRIPTION (Continued)
VSS VSS P52 P57 P02 P20 P03 P13 P12 P46 N/C P47 N/C P11 P10 P01 P00 60 59 58 57 56 55 54
9 P21 P22 P23 P24 P50 P51 /DS P53 P54 R//RL P56 R//W N/C P25 P26 P27 P04 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 PREF1 P36 P37 P35 /RESET VSS P62 P55 N/C P63 /AS P61 P60 P34 P33 P32 P31
Z86E74/L74 PLCC
53 52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 XTAL2 XTAL1 P06 P14 P15 P07 P40 P41 P42 P43 P44 P45 P16 VDD VDD P05 P17
Z86E74 (Standard Mode) Z86L74 68-Pin PLCC Pin Assignments
5
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
ABSOLUTE MAXIMUM RATINGS
Symbol VCC TSTG TA Description Min Max +7.0 +150 Units V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Supply Voltage (*) -0.3 Storage Temp. -65 Oper. Ambient Temp.
Notes: * Voltage on all pins with respect to GND. See Ordering Information.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load).
From Output Under T est
I
150 pF
Test Load Diagram
CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance Max 12 pF 12 pF 12 pF
6
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
DC CHARACTERISTICS (Z86E73/E74)
TA = 0C to +70C Min Max 7 7 VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC 1.3 2.5 0.5 0.9 1.7 3.7 Typ @ 25C
Sym
Parameter Max Input Voltage
VCC 4.0V 5.5V 4.0V 5.5V
Units V V V V V V V V V V V V V V V V V V V V V V
Conditions IIN 250 A IIN 250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes [3]
VCH
Clock Input High Voltage
0.9 VCC 0.9 VCC VSS - 0.3 VSS- 0.3 0.7 VCC 0.7 VCC VSS - 0.3 VSS - 0.3 VCC - 0.4 VCC - 0.4 0.7 0.7
VCL
Clock Input Low Voltage
40V 5.5V
VIH VIL VOH1 VOH2 VOL1 VOL2
Input High Voltage Input Low Voltage Output High Voltage Output High Voltage (P36, P37) Output Low Voltage Output Low Voltage
4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V
IOH = -0.5 mA IOH = -0.5 mA IOH = -7 mA IOH ,= -7 mA IOL = 1.0 mA IOL = 4.0 mA IOL = 2.0 mA 3 Pin Max IOL = 8.0 mA 3 Pin Max IOL = 10 mA IOL = 10 mA 2 O/P only
[10] [10]
0.4 0.4 0.8 0.8 0.8 0.8 0.8 VCC 0.8 VCC VSS - 0.3 VSS - 0.3 VCC VCC 0.2 VCC 0.2 VCC 25 25 1 1 1 1 -45 -55 10 15 100 300
0.2 0.1 0.3 0.5 0.3 0.5 1.5 3.0 0.5 0.9 10 10 <1 <1 <1 <1 -20 -30 4 10 10 10
VOL2
Output Low Voltage (P20-P22, P36, P00, P01, P07) Reset Input High Voltage Reset Input Low Voltage Comparator Input Offset Voltage Input Leakage Output Leakage Reset Input Current Supply Current
4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V
[9] [9]
VRH VRl VOFFSET IIL IOL IIR ICC
mV mV A A A A A A mA mA A A VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC
-1 -1 -1 -1
@ 8.0 MHz @ 8.0 MHz @ 32 kHz @ 32 kHz
[4, 5] [4, 5] [4, 5,11] [4, 5,11]
7
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
DC CHARACTERISTICS (Z86E73/E74) (Continued)
TA = 0C to +70C Min Max 3 Typ @ 25C 1
Sym ICC1
Parameter Standby Current
VCC 4.0V
Units mA
Conditions HALT Mode VIN = OV, VCC @ 8.0 MHz HALT Mode VIN = OV, VCC @ 8.0 MHz Clock Divide-by-16 @ 8.0 MHz Clock Divide-by-16 @ 8.0 MHz STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is Running STOP Mode VIN = OV, VCC WDT is Running
Notes [3] [4,5]
5.5V
5
4
mA
[4,5]
4.0V 5.5V ICC2 Standby Current 4.0V
2 4 8
0.8 2.5 2
mA mA A A A A
[4,5] [4,5] [6,8]
5.5V
10
3
[6,8]
4.0V
500
310
[6,8]
5.5V
800
600
[6,8]
TPOR VLV
Notes: [1] ICC1
Power-On Reset VCC Low Voltage Protection
4.0V 5.5V
15 5
75 20 3.3
13 7 2.75
ms ms V
8 MHz max Ext. CLK Freq.
[7]
Typ
Max
Unit
Frequency 8.0 MHz 8.0 MHz
Crystal/Resonator 3.0 mA 5 mA External Clock Drive 0.3 mA 5 mA [2] GND = 0V. [3] 4.0V to 5.5V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1 = CL2 = 100 pF. [6] Same as note [4] except inputs at VCC. [7] The VLV increases as the temperature decreases. [8] Oscillator stopped. [9] Two outputs at a time, independent to other outputs. [10] One at a time. [11] 32 kHz clock driver input.
8
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
DC CHARACTERISTICS (Z86L73/L74)
TA = 0C to +70C Min Max 7 7 VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC 1.3 2.5 0.5 0.9 1.7 3.7 Typ @ 25C
Sym
Parameter Max Input Voltage
VCC 2.0V 3.9V 2.0V 3.9V
Units V V V V V V V V V V V V V V V V V V V V V V
Conditions IIN 250 A IIN 250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes [3]
VCH
Clock Input High Voltage
0.9 VCC 0.9 VCC VSS - 0.3 VSS- 0.3 0.7 VCC 0.7 VCC VSS - 0.3 VSS - 0.3 VCC - 0.4 VCC - 0.4 0.7 0.7
VCL
Clock Input Low Voltage
2.0V 3.9V
VIH VIL VOH1 VOH2 VOL1 VOL2
Input High Voltage Input Low Voltage Output High Voltage Output High Voltage (P36, P37) Output Low Voltage Output Low Voltage
2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V
IOH = -0.5 mA IOH = -0.5 mA IOH = -7 mA IOH ,= -7 mA IOL = 1.0 mA IOL = 4.0 mA IOL = 2.0 mA 3 Pin Max IOL = 8.0 mA 3 Pin Max IOL = 10 mA IOL = 10 mA 2 O/P only
[10] [10]
0.4 0.4 0.8 0.8 0.8 0.8 0.8 VCC 0.8 VCC VSS - 0.3 VSS - 0.3 VCC VCC 0.2 VCC 0.2 VCC 25 25 1 <1 1 1 -45 -55 10 15 100 300
0.2 0.1 0.3 0.5 0.3 0.5 1.5 3.0 0.5 0.9 10 10 <1 A <1 <1 -20 -30 4 10 10 10
VOL2
Output Low Voltage (P20-P22, P36, P00, P01, P07) Reset Input High Voltage Reset Input Low Voltage Comparator Input Offset Voltage Input Leakage 3.9V Output Leakage Reset Input Current Supply Current
2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V -1 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V
[9] [9]
VRH VRl VOFFSET IIL IOL IIR ICC
mV mV A VIN = OV, VCC VIN = OV, VCC A VIN = OV, VCC A VIN = OV, VCC A A mA mA A A
-1 1 -1 -1
@ 8.0 MHz @ 8.0 MHz @ 32 kHz @ 32 kHz
[4, 5] [4, 5] [4, 5,11] [4, 5,11]
9
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
DC CHARACTERISTICS (Z86L73/L74) (Continued)
TA = 0C to +70C Min Max 3 Typ @ 25C 1
Sym ICC1
Parameter Standby Current
VCC 2.0V
Units mA
Conditions HALT Mode VIN = OV, VCC @ 8.0 MHz HALT Mode VIN = OV, VCC @ 8.0 MHz Clock Divide-by-16 @ 8.0 MHz Clock Divide-by-16 @ 8.0 MHz STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is Running STOP Mode VIN = OV, VCC WDT is Running
Notes [3] [4,5]
3.9V
5
4
mA
[4,5]
2.0V 3.9V ICC2 Standby Current 2.0V
2 4 8
0.8 2.5 2
mA mA A A A A
[4,5] [4,5] [6,8]
3.9V
10
3
[6,8]
2.0V
500
310
[6,8]
3.9V
800
600
[6,8]
TPOR VLV
Power-On Reset VCC Low Voltage Protection
2.0V 3.9V
15 5
75 20 2.15
13 7 1.7
ms ms V
8 MHz max Ext. CLK Freq.
[7]
Notes: [1] ICC1
Typ
Max
Unit
Frequency 8.0 MHz 8.0 MHz
Crystal/Resonator 3.0 mA 5 mA External Clock Drive 0.3 mA 5 mA [2] GND = 0V. [3] 2.0V to 3.9V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1 = CL2 = 100 pF. [6] Same as note [4] except inputs at VCC. [7] The VLV increases as the temperature decreases. [8] Oscillator stopped. [9] Two outputs at a time, independent to other outputs. [10] One at a time. [11] 32 kHz clock driver input.
10
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram
R//W
13 12 19
Port 0, /DM
16 8 3
20
Port 1
A7 - A0
1 2
D7 - D0 IN
9
/AS
8 4 5 6 11
/DS (Read)
17
10
Port 1
A7 - A0
14
D7 - D0
OUT
15 7
/DS (Write)
External I/O or Memory Read/Write Timing
11
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
AC CHARACTERISTICS (Z86E73/E74) External I/O or Memory Read and Write Timing Table
VCC Note [3] 4.0V 5.5V 2.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V TA = 0C to +70C 8.0 MHz Min Max 55 55 70 70 400 400 80 80 0 0 300 300 165 165 260 260 0 0 85 95 60 70 70 70 70 70 80 80 70 80 475 475 100 100 55 55 70 70 70 70
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS Td TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) TdDS(DM) ThDS(A)
Parameter Address Valid to /AS Rising Delay /AS Rising to Address Float Delay /AS Rising to Read Data Required Valid /AS Low Width Address Float to /DS Falling /DS (Read) Low Width /DS (Write) Low Width /DS Falling to Read Data Required Valid Read Data to /DS Rising Hold Time /DS Rising to Address Active Delay /DS Rising to /AS Falling Delay R//W Valid to /AS Rising Delay /DS Rising to R//W Not Valid Write Data Valid to /DS Falling (Write) Delay /DS Rising to Write Data Not Valid Delay Address Valid to Read Data Required Valid /AS Rising to /DS Falling Delay /DM Valid to /AS Falling Delay /DS Rise to /DM Valid Delay /DS Rise to Address Valid Hold Time
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes [2] [2] [1, 2] [2]
[1, 2] [1, 2] [1, 2] [2] [2] [2] [2] [2] [2] [2] [1, 2] [2] [2]
Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] 4.0V to 5.5V. Standard Test Load. All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
12
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
AC CHARACTERISTICS (Z86L73/L74) External I/O or Memory Read and Write Timing Table
VCC Note [3] 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V TA = 0C to +70C 8.0 MHz Min Max 55 55 70 70 400 400 80 80 0 0 300 300 165 165 260 260 0 0 85 95 60 70 70 70 70 70 80 80 70 80 475 475 100 100 55 55 70 70 70 70
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS Td TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) TdDS(DM) ThDS(A)
Parameter Address Valid to /AS Rising Delay /AS Rising to Address Float Delay /AS Rising to Read Data Required Valid /AS Low Width Address Float to /DS Falling /DS (Read) Low Width /DS (Write) Low Width /DS Falling to Read Data Required Valid Read Data to /DS Rising Hold Time /DS Rising to Address Active Delay /DS Rising to /AS Falling Delay R//W Valid to /AS Rising Delay /DS Rising to R//W Not Valid Write Data Valid to /DS Falling (Write) Delay /DS Rising to Write Data Not Valid Delay Address Valid to Read Data Required Valid /AS Rising to /DS Falling Delay /DM Valid to /AS Falling Delay /DS Rise to /DM Valid Delay /DS Rise to Address Valid Hold Time
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes [2] [2] [1, 2] [2]
[1, 2] [1, 2] [1, 2] [2] [2] [2] [2] [2] [2] [2] [1, 2] [2] [2]
Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] 2.0V to 3.9V. Standard Test Load. All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
13
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
AC CHARACTERISTICS Additional Timing Diagram
1 3
Clock
2 7 7 2 3
T
IN
4 6 5
IRQ
N
8 9
Clock Setup
11
Stop Mode Recovery Source
10
Additional Timing
14
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
AC CHARACTERISTICS (Z86E73/E74) Additional Timing Table
TA = 0C to +70C 8.0 MHz Min Max 121 121 DC DC 25 25
No 1 2 3 4 5 6 7 8A 8B 9 10
Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Twsm
Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Timers Interrupt Request Low Time Int. Request Low Time Interrupt Request Input High Time Stop-Mode Recovery Width Spec
VCC Note [3] 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V
Units ns ns ns ns ns ns ns ns
Notes [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1]
37 37 100 70 3TpC 3TpC 8TpC 8TpC 100 100 100 70 3TpC 3TpC 3TpC 3TpC 12 12 5TpC 5TpC 5TpC 5TpC 75 20 150 40 300 80 1200 320
ns ns ns ns
[1] [1] [1, 2] [1, 2] [1, 3] [1, 3] [1, 2] [1, 2]
ns ns
[8] [8] [7] [7] [4] [4] D0 = 0 [5] D1 = 0 [5] D0 = 1 [5] D1 = 0 [5] D0 = 0 [5] D1 = 1 [5] D0 = 1 [5] D1 = 1 [5]
11 12
Tost Twdt
Oscillator Start-up Time Watch-Dog Timer Delay Time
(5 ms) (10 ms) (20 ms) (80 ms)
12 5 25 10 50 20 225 80
ms ms ms ms ms ms ms ms
Notes: [1] Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request through Port 3 (P33-P31). [3] Interrupt request through Port 3 (P30). [4] SMR - D5 = 0. [5] Reg. WDTMR. [6] 4.0V to 5.5V. [7] Reg. SMR - D5 = 0. [8] Reg. SMR - D5 = 1.
15
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
AC CHARACTERISTICS (Z86L73/L74) Additional Timing Table
TA = 0C to +70C 8.0 MHz Min Max 121 121 DC DC 25 25
No 1 2 3 4 5 6 7 8A 8B 9 10
Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Twsm
Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Timers Interrupt Request Low Time Int. Request Low Time Interrupt Request Input High Time Stop-Mode Recovery Width Spec
VCC Note [3] 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V
Units ns ns ns ns ns ns ns ns
Notes [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1]
37 37 100 70 3TpC 3TpC 8TpC 8TpC 100 100 100 70 3TpC 3TpC 3TpC 3TpC 12 12 5TpC 5TpC 5TpC 5TpC 75 20 150 40 300 80 1200 320
ns ns ns ns
[1] [1] [1, 2] [1, 2] [1, 3] [1, 3] [1, 2] [1, 2]
ns ns
[8] [8] [7] [7] [4] [4] D0 = 0 [5] D1 = 0 [5] D0 = 1 [5] D1 = 0 [5] D0 = 0 [5] D1 = 1 [5] D0 = 1 [5] D1 = 1 [5]
11 12
Tost Twdt
Oscillator Start-up Time Watch-Dog Timer Delay Time
(5 ms) (10 ms) (20 ms) (80 ms)
12 5 25 10 50 20 225 80
ms ms ms ms ms ms ms ms
Notes: [1] Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request through Port 3 (P33-P31). [3] Interrupt request through Port 3 (P30). [4] SMR - D5 = 0. [5] Reg. WDTMR. [6] 2.0V to 3.9V. [7] Reg. SMR - D5 = 0. [8] Reg. SMR - D5 = 1.
16
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
AC CHARACTERISTICS Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
1 3
2
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Output Handshake Timing
17
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
AC CHARACTERISTICS (Z86E73/E74) Handshake Timing Table
TA = 0C to +70C 8.0 MHz Min Max 0 0 160 115 155 110 160 115 120 80 0 0 63 63 0 0 160 115 110 80 110 80
No 1 2 3 4 5 6 7 8 9 10 11
Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDYO(DAV) TdDO(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV)
Parameter Data In Setup Time Data In Hold Time Data Available Width DAV Falling to RDY Falling Delay DAV Rising to RDY Falling Delay RDY Rising to DAV Falling Delay Data Out to DAV Falling Delay DAV Falling to RDY Falling Delay RDY Falling to DAV Rising Delay RDY Width RDY Rising to DAV Falling Delay
VCC Note [3] 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V
Data Direction IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
Note: [3] 4.0V to 5.5V.
18
PRELIMINARY
Z86E73/E74/L73/L74 CP95LVO0801
AC CHARACTERISTICS (Z86L73/L74) Handshake Timing Table
TA = 0C to +70C 8.0 MHz Min Max 0 0 160 115 155 110 160 115 120 80 0 0 63 63 0 0 160 115 110 80 110 80
No 1 2 3 4 5 6 7 8 9 10 11
Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDYO(DAV) TdDO(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV)
Parameter Data In Setup Time Data In Hold Time Data Available Width DAV Falling to RDY Falling Delay DAV Rising to RDY Falling Delay RDY Rising to DAV Falling Delay Data Out to DAV Falling Delay DAV Falling to RDY Falling Delay RDY Falling to DAV Rising Delay RDY Width RDY Rising to DAV Falling Delay
VCC Note [3] 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V
Data Direction IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
Note: [3] 2.0V to 3.9V.
19

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